The maximum achievable accuracy-speed performance of any A/D converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain, and/or component mismatch. When designing high-speed, high-accuracy A/D converters, these limitations impose stringent demands on building blocks, leading to prolonged design time and lower yield.
Many non-ideal effects can be compensated for by using calibration, which relaxes the demands on the building blocks while increasing the overall performance. The trend today is to employ calibration which operates on the digital output of the A/D converter, since digital signal processing is robust and can be implemented at a low cost due to the scaling of modern CMOS processes. However, the difficulty is often how to accurately acquire calibration coefficients to be used in the calibration algorithm that makes up for the non-ideal effects of the analog components.
A popular and efficient method to determine the calibration coefficients for pipeline, sub-ranging and cyclic A/D converters employs switching of the internal digital-to-analog converter (D/A converter) elements of the stages to be calibrated by specific calibration test sequences to be able to characterize the critical components and extract calibration coefficients, see [1].
To acquire calibration coefficients, the normal digital thermometer code from an A/D sub-converter to the corresponding D/A sub-converters is replaced by the calibration test sequence. By this arrangement, each D/A sub-converter element can be controlled by the calibration circuitry and the response and weight of each D/A sub-converter element can measured by the resolution and accuracy of the succeeding stages. Once the errors from finite gain amplifiers and the D/A sub-converter element mismatches have been captured, they can be removed from the digital output. The calibration procedure usually starts at a certain stage in the pipeline chain and moves forward to the first stage. Thereby the accuracy of the measuring device is increasing as the calibration process proceeds. Ideally, there is no limitation in the achievable accuracy for a pipeline A/D converter with an infinite number of pipeline stages. However, noise, drift, and non-linear behavior will restrict the achievable accuracy in physical implementations. The starting stage of the calibration process is typically the stage where the non-ideal errors become in parity with the quantization error of the later stages used for the measurements. Since the switching of the D/A converter elements is performed at normal clock rate, the internal dynamic behavior is also monitored and errors from imperfect settling are suppressed as well. A similar calibration procedure is used for cyclic converters, but here the data circulates so that the stage that is calibrated is also used for the measurements.
A problem with the described method is that extra logic is required on the time critical thermometer code bus. This results in an extra signal delay, which has a negative impact on the maximal achievable sample rate.